Francisco Pereira

I am a PhD student at Instituto Superior Técnico, University of Lisbon with a Carnegie Mellon University affiliation and a researcher at INESC-ID. I am advised by Professors Luis Pedrosa, Fernando Ramos, and Justine Sherry.

My research interests lie in between Systems and Networking, ranging from software Network Functions to programmable network accelerators such as programmable switches, FPGAs, and SmartNICs. My ongoing research focuses on modeling Network Functions and automatically synthesizing modifications to them, be it to improve overall performance or offloading them to network accelerators.

Lately I've been working on a new project that tests agentic capabilities in the context of network management. We are largely interested in knowing if agents can effectively manage the Internet as a whole.

Also, I have a deep love for horror movies. If you have any recommendations, send them my way!

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In 2003, Clark et al. proposed the "knowledge plane", a layer of intelligent agents that share rich information about network state in order to collaboratively manage the Internet across administrative boundaries. The technology of the day lacked the two capabilities it demanded most: reasoning and unstructured communication. Thus, automated network management has remained largely confined to single domains, while interdomain problems are still resolved by human operators on the phone. We argue that agentic large language models can finally unlock the potential of the knowledge plane, but that doing so will require solving new research problems that arise particularly in this decentralized, multi-agent, coopetitive setting that have received limited attention in the literature thus far.

To support high-performance network functions, recent work has explored hybrid architectures that combine the flexibility of general-purpose processors with the performance of the PISA switch architecture. These designs partition code and state between switch platforms and general-purpose servers in pursuit of a "best of both worlds" design. However, integrating two separate platforms leads to the age-old challenge of ensuring high throughput and low latency while keeping distributed state consistent. We propose a new, tightly-coupled architecture called SwitchNIC that guarantees consistent state between switch and general-purpose processor, while offering 99th percentile packet latency of 6 𝜇s. The key to SwitchNIC’s performance is a novel, "on-path" state replication protocol, with latency further tightened by implementing general-purpose processing on locally-integrated ARM cores. We prototype SwitchNIC by deploying its state replication algorithms on a Tofino switch with Ethernet-attached ARM-based SmartNICs. SwitchNIC achieves up to 5.2× better energy efficiency and 6.4× better processing latency than server-based systems, none of which completely and correctly support shared state between platforms.

Software network functions (NFs) trade-off flexibility and ease of deployment for an increased challenge of performance. The traditional way to increase NF performance is by distributing traffic to multiple CPU cores, but this poses a significant challenge: how to parallelize an NF without breaking its semantics? We propose Maestro, a tool that analyzes a sequential implementation of an NF and automatically generates an enhanced parallel version that carefully configures the NIC’s Receive Side Scaling mechanism to distribute traffic across cores, while preserving semantics. When possible, Maestro orchestrates a shared-nothing architecture, with each core operating independently without shared memory coordination, maximizing performance. Otherwise, Maestro choreographs a fine-grained read-write locking mechanism that optimizes operation for typical Internet traffic. We parallelized 8 software NFs and show that they generally scale-up linearly until bottlenecked by PCIe when using small packets or by 100 Gbps line-rate with typical Internet traffic. Maestro further outperforms modern hardware-based transactional memory mechanisms, even for challenging parallel-unfriendly workloads.

Francisco Pereira

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Recent publications

Instantiating the Knowledge Plane

SwitchNIC: An Hybrid Architecture for Network Functions with Fast and Consistent Shared State

Automatic Parallelization of Software Network Functions

Automatic Generation of Network Function Accelerators Using Component-Based Synthesis